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-- How much memory can the Palm OS handle? (http://discussion.visorcentral.com/vcforum/showthread.php?threadid=10572)

With the news about a possible 16mb springboard module and even a 16mb RAM upgrade I was wondering if anyone out there knows what the limitations of the Palm OS are regarding memory. Can the Palm OS really handle 16mb of RAM and a 16mb springboard? What would this do to speed? Are there differences between OS 3.1H and 3.5H? As a physician that carries alot of reference data, my VDx with 8mb springboard is full and I want more room!!

Thanks.

Hardware CPU not OS

The ram is limited by the CPU not the Palm OS. I remember reading that the older Motorola processors are limited to 8MB RAM and 8MB of flash RAM.

The new Visors (Prism and Platinum) uses the 33 MHz Motorola Dragonball VZ processor and I beveive that I read somewhere that it supports 32MB of RAM. I am not sure if that is split amount flash and non.

Re: Hardware CPU not OS

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Originally posted by pda4you
The ram is limited by the CPU not the Palm OS. I remember reading that the older Motorola processors are limited to 8MB RAM and 8MB of flash RAM...

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Well, if you want to know how much memory the palm OS can handle, it's 2GB's. But I don't think that well see that anytime soon in PDA's (unless there made by Micro$oft)

BEN

Thanks. So the upcoming 16mb springboard is likely to really happen. For my purposes I can do a lot with a 16mb springboard as I am mostly in need of space for large medical databases and most of them (e.g. from handheldmed, K2, Tealpoint, etc) are fully flash compatible. I hope the 16mb module gets here from Hong Kong soon.

One friend bought a TRG Pro.

Another friend bought an Olympus Camera with an IBM 340MB CF microdrive.

They plugged the microdrive into the TRG Pro and it picked up 340MB of memory.

I'd be interested to see the Springboard-CF adapter working with the IBM 1GB CF microdrive.

I think they should make a native 360 GB Superdrive Springboard, no CF bridge card. That would rock.

quote:

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Originally posted by joelforman
Thanks. So the upcoming 16mb springboard is likely to really happen.

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These are the Direct Spec from the Motorolla website

How can the CPU be limited to 8MB?

Static 68EC000 Core Processor-Identical to MC68EC000 Microprocessor
Full Compatibility with MC68000 and MC68EC000
32-Bit internal address bus
-----=====24-Bit external address bus capable of addressing maximum 4 x 16MB blocks with chip selects CSA, CSB and 4 x 4 MB blocks with chip selects CSC, CSD. ====-----
16-Bit on-chip data bus for MC68000 bus operations
Static design allows processor clock to be stopped to provide power savings
2.7 MIPS Performance at 16.58 MHz processor clock
External M68000 Bus interface with selectable bus sizing for 8-bit and 16-bit data ports

I found this in the "Palm OS Programmer's FAQ" under limits:

quote:

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8 MB addressable memory The Dragonball EZ and eariler CPUs can only address 8 MB of memory at a time. This is not a limit in the CPU's instruction set, it's a limit in the CPU's DRAM controller. This limit can be worked around by having more than one separate 8 MB chunk of memory you see this technique used in the original Visor and the Sony Clie, both of which have 8 MB add-on cards available. The TRG units can use even larger Compact Flash cards, but they don't directly access this memory: they move blocks of data to and from the CF card like your desktop computer uses its hard drive. The newer Dragonball VZ chip supports up to 32 MB of memory, but currently no released device has more than 8 MB.

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Re: These are the Direct Spec from the Motorolla website

You need to look into the specification of the chip select signal and the DRAM controller.

CSA, CSB can only be used to select non-DRAM memory chips, the maximum size is 4x16MB (4 chip select signals: CSA0, CSA1, CSB0, CSB1, each chip can be as large as 16MB).

CSC, CSD can be used to select non-DRAM chips as well as DRAM chips, but not at the same time. When non-DRAM chips are used, the size can be up to 4x16MB (signals are CSC0, CSC1, CSD0, CSD1). When DRAM chips are used, for DragonBall EZ, the size can be up to 4x4MB; for VZ, the size can be up to 4x16MB (signals are CAS0, CAS1, RAS0, RAS1).

This means EZ can support up to 16M DRAM plus 64M non-DRAM memory, and VZ can support up to 64M DRAM plus 64M non-DRAM memory. However, two DRAM banks are required to make full use of all the capacity. In Visor, their is only one momory bank, so the DRAM limit is 8M for VDX (with EZ CPU) and 32M for VPL and VPR (with VZ CPU).

I guess the Springbboard port makes use of CSB and the ROM use CSA, both are seperated from the DRAM space.

quote:

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Originally posted by klau1
How can the CPU be limited to 8MB?

Static 68EC000 Core Processor-Identical to MC68EC000 Microprocessor
Full Compatibility with MC68000 and MC68EC000
32-Bit internal address bus
-----=====24-Bit external address bus capable of addressing maximum 4 x 16MB blocks with chip selects CSA, CSB and 4 x 4 MB blocks with chip selects CSC, CSD. ====-----
16-Bit on-chip data bus for MC68000 bus operations
Static design allows processor clock to be stopped to provide power savings
2.7 MIPS Performance at 16.58 MHz processor clock
External M68000 Bus interface with selectable bus sizing for 8-bit and 16-bit data ports

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It's not an addressing limitation. It's a refresh limitation. DRAM (dynamic RAM) needs to be read and rewritten continuously to avoid losing data. SRAM (static RAM) uses flip-flops rather than capacitors for data storage (basically, anyway), but that makes the cells larger and more complex, which in turn makes SRAM much more expensive.

The built-in DRAM controller in the EZ can only provide refresh for 8M of DRAM. To get more than 8M you need an external DRAM controller or SRAM.

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