xjx
Member
Registered: Dec 1999
Location: Atlanta, GA
Posts: 114 |
Re: These are the Direct Spec from the Motorolla website
You need to look into the specification of the chip select signal and the DRAM controller.
CSA, CSB can only be used to select non-DRAM memory chips, the maximum size is 4x16MB (4 chip select signals: CSA0, CSA1, CSB0, CSB1, each chip can be as large as 16MB).
CSC, CSD can be used to select non-DRAM chips as well as DRAM chips, but not at the same time. When non-DRAM chips are used, the size can be up to 4x16MB (signals are CSC0, CSC1, CSD0, CSD1). When DRAM chips are used, for DragonBall EZ, the size can be up to 4x4MB; for VZ, the size can be up to 4x16MB (signals are CAS0, CAS1, RAS0, RAS1).
This means EZ can support up to 16M DRAM plus 64M non-DRAM memory, and VZ can support up to 64M DRAM plus 64M non-DRAM memory. However, two DRAM banks are required to make full use of all the capacity. In Visor, their is only one momory bank, so the DRAM limit is 8M for VDX (with EZ CPU) and 32M for VPL and VPR (with VZ CPU).
I guess the Springbboard port makes use of CSB and the ROM use CSA, both are seperated from the DRAM space.
quote: Originally posted by klau1
How can the CPU be limited to 8MB?
Static 68EC000 Core Processor-Identical to MC68EC000 Microprocessor
Full Compatibility with MC68000 and MC68EC000
32-Bit internal address bus
-----=====24-Bit external address bus capable of addressing maximum 4 x 16MB blocks with chip selects CSA, CSB and 4 x 4 MB blocks with chip selects CSC, CSD. ====-----
16-Bit on-chip data bus for MC68000 bus operations
Static design allows processor clock to be stopped to provide power savings
2.7 MIPS Performance at 16.58 MHz processor clock
External M68000 Bus interface with selectable bus sizing for 8-bit and 16-bit data ports
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